Philippine E-Journals

A SYNTHESIZABLE VHDL MODEL OF A LOSSLESS DATA COMPRESSION CIRCUIT USING RUN LENGTH ENCODING ALGORITHM

Analene Montesines Nagayo | Roderick Yap

Discipline: Engineering

 

Abstract:

This paper presents a synthesizable VHDL model of a Lossless Data Compression Circuit. The technique used/or compressing is the Run Length Encoding (RLE) scheme. RLE reduces strings of repeating data and encode it as two bytes. One byte contains the run value and the other byte contains the run count. A Bitmap file of a black and white image is used as an input data to the VHDL compression program and the performance of the system is analyzed. The obtained compressed data is then used as an input to the VHDL decompression program. Simulation results show that the program was able to restore the original input image data.